While many programs can obtain acceptable performance by simply letting the processor manage its own caching, programs with special requirements may obtain dramatically improved performance by giving the processor explicit instructions and manipulating the cache directly. More typically, boot firmware may need to flush and enable the cache.
Programming the cache on the PowerPC
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That IBM information is also valid for some Motorola PPCs like the MPC740, MPC745, MPC755, …
Precisely controlling the cache is particularly important for embedded design.
For example, the cache is 8 way. If you lock a way in an appropriate manner, you can keep a interruption routine into the cache eternally, thus giving predictable interrupt execution times.
The external cache can also be transformed into a separate private memory area.
On another point, there is no single proper cache flush instruction in the PowerPCs, an equivalent of the x86’s WBINVD ( Write Back and Invalidate ) so the only way to flush it is to fill it with dummy data.
Cache control instructions like DCBZ and DCBTST allows to optimise performance by tweaking cache accesses. DCBZ zeroes a full cache line without doing a single real memory acces whereas DCBTST indicate that a full cache line will be written with new data and there is no need to burst read the cache line before writing into the first word.
@Treza
On another point, there is no single proper cache flush instruction in the PowerPCs, an equivalent of the x86’s WBINVD ( Write Back and Invalidate ) so the only way to flush it is to fill it with dummy data.
Why would you fill the caches with dummy data to flush? Never heard of DCBF, DCBI? Surely you have to go trough a loop for flushing, but no need to fill with dummy data. (BTW I feel it lot more sensible approach than the full cache flush at once.)
You’re right, I agree.
It’s the classical RISC vs microcoded CISC instructions dilemma…
Perhaps I am biased, having been involved with the writing of ap notes at Motorola that have a great deal more meaningful information describing how to use those instructions.
I don’t work for Motorola anymore, but the Freescale web site should contain the best one (my name isn’t on the paper- maybe a search for Kalpesh Gala will locate it). I can’t find it, though, which is weird. The paper involves utilizing the way-locking feature of the 603e, 745, 755, 7445, 7455. Everything that IBM discusses in their paper is explained much better in the Motorola/Freescale app note.
My favorite paper is still:
http://www.freescale.com/files/archives/doc/white_paper/INSTRUCTIN6…