“Judging a book by its cover alone would mean that AMD’s Hammer architecture would be used in the first 64-bit x86 microprocessors. We already know that Intel has taken a route away from x86 for their 64-bit solution, Itanium which uses a new instruction set architecture (ISA) called EPIC. The point of this article is to not only examine the pros and cons of AMD’s extension of the 32-bit x86 ISA but also the rest of the story when it comes to Hammer since there is a lot more to this architecture than a few more registers and greater memory addressability.” Anandtech explains it all for you.
AMD’s Hammer Architecture – Making Sense of it All
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No, why? 😮
“BBC World: Making sense of it all!”
back to sanity.
I look forward to trying out Hammer as I would like to make a 64 bit port of PetrOS, and it looks like it will be easier than with IA64.
A 64 bit address space would be cool for kernel stuff. For e.g. instead of accessing a disk drive in a traditional way, you could memory map the whole drive and let the pager do stuff. It could make for interesting FS driver design.
Also, with recent machines, natively mapping the full physical memory to a flat virtual space can become a problem when you get over a certain threshold. It’s kind of handy to be able to quickly map a given physical page without having to toy with a page descriptor. This is especially important when manipulating page tables, and when you run out of virtual address space to map the physical address space, you have to resort to methods like classifying physical address space by memory use. You would use the section of memory that can be mapped to a virtual range for things like page tables, DMA buffers & such, and the rest you would allocate to pages that you never need to reference as a physical address.
The advantage of a 64 bit address architecture is that this limitation would be removed since the address space is so huge that you would be highly unlikely to exhaust even a small fraction of the virtual address space for such things.
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