For those who are not familiar with Celerity, this is a multi-university effort that has resulted in an open-source manycore RISC-V tiered accelerator chip. The project is part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program which wants to drive the design cycle for custom integrated circuits to weeks and months from years. The Celerity team first presented the chip at Hot Chips 29. Last year, at VLSI 2019, Celerity was back to talk about the PLL and the NoC of its second-generation chip. The presentation was given by Austin Rovinski from the University of Michigan.
I can read the words, but much of this is far too complicated for me to give any meaningful comment.
Parallella Adapteva Epiphany-V ? A 1024 processor 64-bit RISC System… back in 2012.
The Epiphany-V took four years to make, and will never be available commercially. The chip in the article was made as part of an initiative to make chips faster, and was made by a group of universities rather than a company. Also given that the chip in the article is an array of RISC-V processors, I think it’s a much better accomplishment.
The Epiphany was mostly a one man project, much like the Parallax Propeller is. The 16 cores Epiphany-III was the first version that would fund the 1024 ores version that was based on exactly the same principle. As the first version wasn’t the expected success it should have been, the next version was dismissed due to lack of funding. And Darpa recruiting the author.
In 2012 RISC-V was yet nothing to worry about at that time. Now it has matured enough to draw industrial attention.