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you only mention POWER when SPARC is making leaps.... 8)

What I find funny is the fact that they would be better off fixing x86 than continuing to flog a dead horse; there are features in he high end which they would be better off going the full monty and incorporate into their mainstream processsors - MMIO for example.

MMIO? What's that? And how should it be introduced or fixed in x86?

And what I find funny is how many people know precisely what Intel is doing wrong in terms of their strategic and economic decisions. Even when carrying the disadvantage of having just a smidgen less information than the decision makers at Intel.

Information is on wikipedia, as for why? look at the latest conversations regarding SCSI/OpenSolaris and how the lack of MMIO (when compared to SPARC) makes driver writing that little bit more difficult. It would also improve performance, especially on very large configurations.

Intel will be introducing partially when they release their next x86 platform which will have all the components (chipset/processor/etc) virtualisation aware, which should also address any performance issues as well.

It would also be great if the PC market got their act together and finally killed off BIOS; UEFI is here, lets move on. Since moving to Apple, thanks to dropping all the legacy crap, the OS loads faster, there aren't there laundry list of issues which I face etc. part of the Mac's succcess is in the hardware, OpenFirmware avoided the crap of BIOS and UEFI does the same time.

What in god's name are you talking about? x86 systems have supported memory-mapped I/O since forever.

Edited 2007-11-01 04:07

Information is on wikipedia, as for why?

MMIO? As in memory mapped IO? Intel x86 CPUs have had this capability for a long time. Seeing as all their memory traffic goes through a discrete northbridge chip anyway, the main thing for the actual CPU to provide is really the memory access policies to make it useful.

It helps if you actually know what you're talking about, when you're making assertions.


look at the latest conversations regarding SCSI/OpenSolaris and how the lack of MMIO (when compared to SPARC) makes driver writing that little bit more difficult.

I have a feeling you read some thread where people were talking about IOMMUs. Completely different, but again due to the nature of Intel's CPUs, IOMMUs are more a function of the platform. And that's true of ia64 too, Itanium CPUs don't have IOMMUs either. While IBM xseries x86 systems do have IOMMUs, and on the other hand, SGI's ia64 Altix systems don't.

It would also improve performance, especially on very large configurations.

Possible, but not always the case. If devices are capable, there is no big for an IOMMU to improve performance since the days of DAC over slow old 32 bit PCI are over. (Actually using it could reduce performance due to translation management overhead). Memory protection is the main reason for the renewed interest recently.

They probably would like to kill the whole thing asap, but probably don't do it because:
- would give them a lot of headache because contracts;
- would damage their public image with tech partners, tech media and customers (the big ones that really expend money).

After all, Intel did pledge one's faith, they must honor their words, even though they will give more and more incentives to people move away.

"The latest greatest Intanium is manufactured in 90nm technology?! Xeons will be manufactured in 45nm pretty soon! "

The problem is that for processes under 90nm there is still a lot of unknowns regarding electron migration. Which means that sub-90nm processors have a fairly compromised lifetime. In the Xeon non mission critical market place that expects replacement in less that 18 months. That is not an issue. On top of that the cache design for the Itanium is fairly hand tuned, and it is not so easily portable to other processes. And the gains of shrinking are not offset by the reduced performance of the resulting cache at 65nm. Even at 1.5Ghz, an Itanium2 still manages top FP scores. Not too shabby.


In the mission critical segment that IA64, and some other manufacturers target. Speed is not as important as it is being up for eons of time, and have parts not fail for years of 24/7 operation. That is why a lot of IBM mainframes are not using Power6 but rather some "unsexy" 130nm processors. Because even at 90nm electron migration may be considered too risky.

There is a method behind the madness...

Edited 2007-11-01 09:39

"The problem is that for processes under 90nm there is still a lot of unknowns regarding electron migration. Which means that sub-90nm processors have a fairly compromised lifetime. In the Xeon non mission critical market place that expects replacement in less that 18 months. That is not an issue. On top of that the cache design for the Itanium is fairly hand tuned, and it is not so easily portable to other processes. And the gains of shrinking are not offset by the reduced performance of the resulting cache at 65nm. Even at 1.5Ghz, an Itanium2 still manages top FP scores. Not too shabby.


In the mission critical segment that IA64, and some other manufacturers target. Speed is not as important as it is being up for eons of time, and have parts not fail for years of 24/7 operation. That is why a lot of IBM mainframes are not using Power6 but rather some "unsexy" 130nm processors. Because even at 90nm electron migration may be considered too risky.

There is a method behind the madness... "



Yes, enteprise machines are more conservative, but you are full of crap wrt IBM:

power 6 - 65 nm
http://www.research.ibm.com/journal/rd/516/le.html

z6 - 65 nm
http://www2.hursley.ibm.com/decimal/IBM-z6-mainframe-microprocessor...

The previous power and mainframe processors were 90 nm.

"Yes, enteprise machines are more conservative, but you are full of crap wrt IBM:"

Before you use such language, I recommend you understand what you posted.

The current offering from ibm, the Z9, is a 90nm process just like Itanium. For the reasons I cited. The Z6 will come out in 65nm just as the new IA64 65nm parts roll out in a year or two. The Z-series are the types of systems targeted by the superdomes and integrity series from HP. Z-series don't use Power6, but the z9/z6 which have some commonalities but are different enough to be their own beasts.

The consumer parts go in a more aggressive process shrinking than the carrier-level grade stuff that is usually 1 or 2 process geometries behind. The reasons being some of the ones I cited before on why the IA64 and Z-series stuff are fabbed in less "sexy" 90nm.

http://www.research.ibm.com/journal/rd/511/poindexter.html

So rather than say I am full of crap, just bother to read the links you referred. In any case, I get a chuckle about all this nm stuff when most people in this forum don't even understand the basic operation of a transistor :-)

"Before you use such language, I recommend you understand what you posted.

The current offering from ibm, the Z9, is a 90nm process just like Itanium. For the reasons I cited. The Z6 will come out in 65nm just as the new IA64 65nm parts roll out in a year or two. The Z-series are the types of systems targeted by the superdomes and integrity series from HP. Z-series don't use Power6, but the z9/z6 which have some commonalities but are different enough to be their own beasts.

The consumer parts go in a more aggressive process shrinking than the carrier-level grade stuff that is usually 1 or 2 process geometries behind. The reasons being some of the ones I cited before on why the IA64 and Z-series stuff are fabbed in less "sexy" 90nm.

http://www.research.ibm.com/journal/rd/511/poindexter.html

So rather than say I am full of crap, just bother to read the links you referred. In any case, I get a chuckle about all this nm stuff when most people in this forum don't even understand the basic operation of a transistor :-)"




I read what I posted. In fact, I attended the z6 presentation.

Let's start from scratch. Here is what you originally posted:




"That is why a lot of IBM mainframes are not using Power6 but rather some "unsexy" 130nm processors. Because even at 90nm electron migration may be considered too risky. "




I never disagreed with your argument. I took issue with the numbers that you tried to use to support your argument. They are just wrong. The z9 mainframes that IBM is selling today with their bluefire processors are 90 nm. They are not "unsexy" 130 nm. It's nice that you corrected yourself in your reply

(which is still a good thing, even if it didn't go the way intel hoped)

What's good about inventing a crappy new architecture?

Intel never invented the architecture, it was HP who did, Intel wanted a high end, high margin chip - HP had it, HP no longer wanted to be in the chip business, so they sold off what ever assets they had to Intel.

Intel is still developing it, but basically its a dead end for Intel. They have realised that although x86 is ugly, its going to be the architecture that never died. Btw, this isn't the first time a superior architecture has gone up against x86 and failed.

Alpha was a superior architecture that went up against x86 and failed. IA64... just failed...

Edited 2007-11-01 04:10

Alpha superior in what aspect?

AXP was a very compromised architecture, a lot of people seem to take that as "elegant." By the time the 21364 came along, it was clear that it would take a significant investment to make it competitive in the post GHz era. The 21464 was a complete bloated pig that was almost impossible to fab. I love alternative architectures, however one must be realistic...

It is usually those who know the least about the subject who get to judge what "elegance" is. To this day I still get a kick about the typical fanboy complaining about the "ugliness" of the x86 and how PPC is the shit because it is "RISC!" never mind that those people can't barely write a half assed program in C much less code anything in assembler. And don't get me started on the idiots who couldn't pass an intro class to computer architecture, but they get to weigh in on the latest design from a top architecture bureau.

Itanium is geared towards a segment of computing, about which most people in this website have little to no knowledge. IA64 has been fantastically successful for HP, the superdomes et al are making a shitload of money for HP. In that context, Itanium is doing very well. Not only that but even at 1.5GHz it achieves some impressive performance numbers.

There is more to computer architecture than being able to assemble a computer from whatever parts you just bought at Fry's.

[i]Itanium is geared towards a segment of computing, about which most people in this website have little to no knowledge. IA64 has been fantastically successful for HP, the superdomes et al are making a shitload of money for HP. In that context, Itanium is doing very well. Not only that but even at 1.5GHz it achieves some impressive performance numbers. [i]

I BACK YOU UP!

AXP was a very compromised architecture, a lot of people seem to take that as "elegant." By the time the 21364 came along, it was clear that it would take a significant investment to make it competitive in the post GHz era.

We're talking about instruction sets here, not the micro-architectures of particular CPUs. The IA64 ISA itself is just a crappy design. VLIW is a dumb idea for a general-purpose processor, and IA64 is an overly-complex and obscure VLIW at that. Maybe these things weren't obvious when IA64 was designed, but they're painfully obvious now.

Itanium is geared towards a segment of computing, about which most people in this website have little to no knowledge. IA64 has been fantastically successful for HP, the superdomes et al are making a shitload of money for HP. In that context, Itanium is doing very well.

Itanium is a "success" by very limited and compromised criteria. The claims of Itanium "profitability" ignore the huge initial investment into the architecture. Itanium is making an operating profit for HP and Intel, but over the long term history of the product, it has lost money. The former point means it makes sense for HP and Intel to string Itanium along until x86 eats its lunch somewhere down the road, while the latter point means that if Intel and HP could go back in time and never do the whole EPIC thing, they would.

Business considerations aside, IA64 has failed as a piece of technology. Itanium is a reasonable chip for certain applications, but by and large its strengths have f*ck-all to do with IA64 itself. Pretty much the only codes that show EPIC in a good light are certain HPC codes, and while hindsight rationalizers will say otherwise, Intel and HP sure as hell didn't invest billions of dollars into a whole new architecture over a decade and a half to develop an ISA targeting for such a specific niche!

Fundamentally, IA64 bet on certain things that just didn't pan out. Specifically, mainstream software ecosystems aren't conducive to VLIW designs, the compiler technology to make them effective isn't feasible, and general-purpose software is moving away from the types of contexts in which VLIW makes sense. Things like this happen all the time, really --- technology fails because it makes assumptions about other technology that don't pan out. The only reason IA64 won't die quietly is because Intel and HP really put a lot of money into it, and they want to milk it and at least get some of it back. For the rest of the market, the only thing IA64 really accomplishes is keeping a bunch of compiler research dollars tied up in unproductive endeavors.

Edited 2007-11-01 14:14